In some analog, digital, and mixed-signal systems, critical timing information is present only on one of rising or falling transitions of timing signals such as clock signals. Some of these systems may need to synthesize an output clock signal from two input clock signals, such that the output clock signal transitions on every useful transition of the two input clock signals. Edge selection circuits can be employed for the purpose of synthesizing an output clock from two input clock signals.
For example, FIG. 1 is a timing diagram that generally illustrates an exemplary mode of operation of an edge selection circuit. In FIG. 1, waveform (a) shows a first clock signal CLK1, waveform (b) shows a second clock signal CLK2, and waveform (c) shows an output clock signal CLKOUT that is generated from the two input clock signals. In particular, in FIG. 1, it is assumed that the two input clock signals CLK1 and CLK2 have rising transitions that contain timing information of interest to a given system. The output clock signal CLKOUT is derived from CLK1 and CLK2 such that the rising and falling edges of CLKOUT correspond to the rising edges of CLK1 and CLK2, respectively, as indicated by the dashed arrows.
In many circuits, the overall system performance may be degraded if a clock duty cycle deviates from 50%. For instance, in a high-speed I/O receiver incorporating a half-rate architecture, it is important that the clock have 50% duty cycle for the even and odd data bits to be sampled at uniform time intervals. Otherwise, it would be impossible to find a sampling clock position which is ideal for both even and odd data bits, and the timing margin for detecting error-free data will be eroded. Unfortunately, some circuits (such as CMOS phase interpolators) may generate output clock waveforms with duty cycle distortion while accomplishing their functions.
In order to utilize the functions of such circuits without negative effects on system performance, it is desirable to have a technique capable of correcting such duty cycle distortion. If complementary clocks are processed by identical circuits (e.g., phase interpolators), their outputs may have distorted (non-50%) duty cycles. But to the extent that the circuits (and therefore the duty cycles) match, the time spacing from the rising edge of one output to the rising edge of the other output may be exactly one half clock period. In this case, an attractive option for synthesizing a clock with 50% duty cycle is to select only the rising edges of the distorted signals in constructing the final output waveform. An edge selection technique may be especially useful for correcting duty cycle distortion in clock signals.